Global Edge AI & Silicon Interconnect Symposium
Exploring the Frontier of Sub-15-Watt Edge Inference
The Global Edge AI and Silicon Interconnect Symposium convenes hardware architects, robotics systems engineers, and neural compiler developers to explore high-throughput reasoning deployed directly onto resource-constrained physical endpoints.
As autonomous industrial fleets and sovereign medical systems demand local physical reasoning without cloud egress roundtrips, the symposium focuses on the co-design of silicon topology, ternary quantization formats, and memory-coherent buses.
Symposium Sessions & Live Demonstrations
Attendees will experience real-world benchmarks, hardware demonstrations, and technical teardowns including:
- Heterogeneous SoC Architecture: Integrating low-power RISC-V control cores with systolic matrix accelerators on unified memory pools.
- Non-Volatile In-Memory Compute: Reducing energy consumption per inference pass by executing weights directly within resistive RAM arrays.
- Thermal Envelopes & Acoustic Limits: Engineering passively cooled ruggedized nodes capable of continuous 32B model inference in demanding industrial environments.
Exhibition Hall & Silicon Clinics
The interactive exhibit hall features reference prototype boards from leading foundries, accompanied by hands-on firmware toolchain clinics allowing engineers to flash and evaluate custom quantized neural kernels in real time.
